1. Technical Field
The embodiments described herein relate to a phase synchronization apparatus, and more particularly, to a phase locked loop (PLL) circuit used in a semiconductor integrated circuit (IC) device.
2. Related Art
As operational speeds of semiconductor IC devices have gradually increased, frequencies of external clock signals used with such devices have also increased. As a result, frequencies of internal clock signals have also increased. Accordingly, conventional semiconductor IC devices often use a phase locked loop (PLL) circuit instead of a delayed locked loop (DLL) circuit as a clock phase synchronization apparatus in order to improve adaptability to high-frequency clock signals. The PLL circuit can be applied in various fields, such as a wired and wireless communication systems including RF systems, and is commonly used as, e.g., a phase controller, a frequency synchronizer, and a time-division system.
In general, the PLL circuit includes a phase detector, a charge pump, a low-pass filter, a voltage controlled oscillator (VCO), and a clock divider. Here, a gain of the VCO, i.e., a ratio of a control voltage to an output clock signal that is transmitted through a loop filter, is an important element for determining an operating characteristic of the PLL circuit. A conventional PLL circuit primarily uses a voltage controlled oscillator (VOC) having a large gain, which is intended to implement a phase fixing operation having short locking time. However, such a voltage controlled oscillator (VOC) having a large gain is problematic in that operational stability deteriorates because frequency band sensitively varies due to a change in voltage. Meanwhile, when a voltage controlled oscillator having a small gain is used in order to overcome this problem, the operational stability is improved, but the locking time is extended and an available frequency band is narrowed.
Accordingly, the operational performance of a conventional PLL circuit depends on the gain of the voltage controlled oscillator. Thus, operational stability in such a device is achieved using a voltage controlled oscillator having a large gain. Alternatively, a short locking time can be achieved by using the voltage controlled oscillator having a small gain. As conventional semiconductor integrated circuit devices are more commonly used in a high-speed environment, implementation of a high-performance clock phase synchronization apparatus is required. However, a conventional PLL circuit has the above-described technical problems when used in such an environment.